"Double-taps" is not what I see on mine. So it is possible we're solving different problems, or your input signals are different from mine.Again sorry for keeping asking but why is it that the du-seq double taps when the reset trig happens at the same time as a clock pulse. And why is it our diagram fixes this?
The problem I see is that if the reset signal comes from e.g. a clock divider or other signal that follows the main clock/gate, then the first DU-SEQ step will not happen "on the beat" but rather on the next clock pulse (gate).
This is because the reset input on the DU-SEQ is what the designers called a true asynchronous reset — it goes directly to all of the logic chips and locks them into the initial state ignoring all input. Thus, the first step of DU-SEQ's sequence occurs on the first clock rising edge that occurs after the falling edge of reset. The goal of this patch, for me, is to make sure that the clock rising edge happens after the reset falls ("at the same time as reset falls" seems to work too, but that's not guaranteed) so that the first step happens on that first clock pulse that's accompanied by a (shortened) reset pulse.
The ideal way to generate these signals would be to have a sequencing patch/module that fires a reset just before the "beat" that we want it to play the first step on, but that would require something like a step sequencer with an extra output and fine enough steps so that it can insert a reset between the notes we want to hear.